// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s -- panama-verilog | FileCheck %s -check-prefix=VERILOG

import chisel3._
import chisel3.panamalib.option._

// println(lit.utility.panamaconverter.verilogString(???, Set(AddMuxPragmas(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(AddVivadoRAMAddressConflictSynthesisBugWorkaround(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(BlackBoxRootPath(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(BuildMode(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(ChiselInterfaceOutDirectory(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(CkgEnableName(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(CkgInputName(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(CkgModuleName(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(CkgOutputName(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(CkgTestEnableName(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(CompanionMode(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(DisableAggressiveMergeConnections(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(DisableAnnotationsClassless(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(DisableOptimization(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(DisableRandom(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(DisableUnknownAnnotations(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EmitChiselAssertsAsSVA(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EmitOmir(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EmitSeparateAlwaysBlocks(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EnableAnnotationWarning(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EtcDisableInstanceExtraction(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EtcDisableModuleInlining(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(EtcDisableRegisterExtraction(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(ExportChiselInterface(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(ExportModuleHierarchy(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(ExtractTestCode(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(IgnoreReadEnableMem(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(LowerAnnotationsNoRefTypePorts(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(LowerMemories(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(NoDedup(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(OmirOutFile(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(OutputAnnotationFilename(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(OutputFilename(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(PreserveAggregate(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(PreserveValues(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(ReplSeqMem(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(ReplSeqMemFile(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(StripDebugInfo(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(StripFirDebugInfo(???))))
// println(lit.utility.panamaconverter.verilogString(???, Set(VbToBv(???))))